PC Logic¶

This section details the implementation of the Program Counter (PC) logic, covering PC_Logic.v, ProgramCounter.v, and the relevant multiplexing logic for the PC adder within RV.v.

Branch Resolution¶

In Mach-V Version 2, branch and jump instructions are committed in the Mem stage. Moving this logic from Execute to Memory improved timing performance, allowing the design to achieve a clock frequency of 115 MHz.

The microarchitecture consists of two main components:

1. PC Logic Unit: Determines whether a branch is taken based on ALU flags and branch conditions.
2. PC Adder: Computes the next PC value based on the current PC, branch targets, and jump addresses.

PC Logic Unit¶

The PC Logic Unit decides how the next PC value is formed. It uses instruction type and ALU comparison results to generate a 2-bit control signal PCSrc[1:0], which selects the PC update behavior and thus PCSrc[1:0] can indicate whether a branch or jump is taken.

1. PCS (Input)
   • Encodes the instruction category (sequential, branch, JAL, JALR).
   • Combined with ALU flags to decide whether a control transfer is taken.
2. ALUFlags[2:0] = {eq, lt, ltu} (Input)
   • Result of comparisons performed by the ALU.
   • Used mainly for conditional branches (e.g., BEQ, BLT, BLTU).
3. PCSrc[1:0] (Output)
   • Controls how the next PC is computed.

The logic of PC Logic can be summarized in the following table:

PC Adder¶

The PC Adder computes the next address (including the branch target or jump address). Because the commitment happens in the Mem stage, the inputs must be sourced correctly to avoid hazards:

• PC_Base: Selects between the current PC (PCF, PCM) or a register value (RD1M). Note that RD1M is derived from RD1E_Forwarded and latched into the Mem stage pipeline register.
• PC_Offset: Selects between sequential increment (+4) or the branch offset (+ExtImmM).